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VTM 48 EH 020 x 040A00
This is similar in form to Eq. (3), where R OUT is used to
represent the characteristic impedance of the SAC?. However,
in this case a real R on the input side of the SAC is effectively
scaled by K 2 with respect to the output.
Assuming that R = 1 Ω , the effective R as seen from the secondary
side is 0.98 m Ω , with K = 1/32 as shown in Figure 18.
A similar exercise should be performed with the additon of a
capacitor, or shunt impedance, at the input to the SAC. A
switch in series with V IN is added to the circuit. This is depicted
in Figure 19.
Low impedance is a key requirement for powering a high-
current, low-voltage load efficiently. A switching regulation
stage should have minimal impedance, while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit, scaling down series impedance
leading back to the source and scaling up shunt capacitance
(or energy storage) as a function of its K factor squared.
However, these benefits are not useful if the series impedance
of the SAC is too high. The impedance of the SAC must be low
well beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables magnetic
SAC
K = 1/32
IN
Vin
+
–
S
C
SAC?
K = 1/32
OUT
V Vout
components to be small since magnetizing currents remain
low. Small magnetics mean small path lengths for turns. Use of
low loss core material at high frequencies reduces core losses
as well.
The two main terms of power loss in the VTM? module are:
- No load power dissipation (P NL ): defined as the power
used to power up the module with an enabled power
Figure 19 — Sine Amplitude Converter? with input capacitor
A change in V IN with the switch closed would result in a
train at no load.
- Resistive loss (R OUT ): refers to the power loss across the
VTM current multiplier modeled as pure resistive impedance.
change in capacitor current according to the following
equation:
P DISSIPATED = P NL + P ROUT
(10)
I C (t) = C
dV IN
dt
(7)
Therefore,
P OUT = P IN – P DISSIPATED = P IN – P NL – P ROUT
(11)
Assume that with the capacitor charged to V IN , the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
The above relations can be combined to calculate the overall
module efficiency:
I C = I OUT ? K
(8)
η =
P OUT = P IN – P NL – P ROUT
P IN P IN
(12)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
I OUT =
C
K 2
?
dV OUT
dt
(9)
=
V IN ? I IN – P NL – (I OUT ) 2 ? R OUT
V IN ? I IN
)
Writing the equation in terms of the output has yielded a K 2
scaling factor for C, this time in the denominator of the
equation. For a K factor less than unity, this results in an
= 1–
(
P NL + (I OUT ) 2 ? R OUT
V IN ? I IN
effectively larger capacitance on the output when expressed in
terms of the input. With a K=1/32 as shown in Figure 19,
C=1 μF would effectively appear as C=1024 μF when viewed
from the output.
Rev. 2.1
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
6/2012
Page 12 of 16
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